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32m x 16 bit ddr2 synchronous dram (sdram) advanced (rev. 1.4, jun. /2014) features ? jedec standard compliant ? jedec standard 1.8v i/o (sstl_18-compatible) ? power supplies: v dd & v ddq = +1.8v 0.1v ? operating temperature: tc = 0~95 ? supports jedec clock jitter specification ? fully synchronous operation ? fast clock rate: 333/400/533mhz ? differential clock, ck & ck# ? bidirectional single/differential data strobe - dqs & dqs# ? 4 internal banks for concurrent operation ? 4-bit prefetch architecture ? internal pipeline architecture ? precharge & active power down ? programmable mode & extended mode registers ? posted cas# additive latency (al): 0, 1, 2, 3, 4, 5, 6 ? write latency = read latency - 1 t ck ? burst lengths: 4 or 8 ? burst type: sequential / interleave ? dll enable/disable ? off-chip driver (ocd) - impedance adjustment - adjustable data-output drive strength ? on-die termination (odt) ? rohs compliant ? auto refresh and self refresh ? 8192 refresh cycles / 64ms - average refresh period 7.8 s @ 0 Q tc Q +85 3.9 s @ +85 tc Q +95 ? 84-ball 8x12.5x1.2mm (max) fbga - pb and halogen free overview the AS4C32M16D2A-25BCN is a high-speed cmos double-data-rate-two (ddr2), synchronous dynamic random-access memory (sdram) containing 512 mbits in a 16-bit wide data i/os. it is internally configured as a quad bank dram, 4 banks x 8mb addresses x 16 i/os the device is designed to comply with ddr2 dram key features such as posted cas# with additive latency, write latency = read latency -1, off-chip driver (ocd) impedance adjustment, and on die termination(odt) . all of the control and address inputs are s ynchronized with a pair of externally supplied differential clocks. inputs ar e latched at the cross point of differential clocks (ck rising and ck# falling) all i/os are synchronized with a pair of bidirectional strobes (dqs and dqs#) in a source synchronous fashion. the address bus is used to convey row, column, and bank address information in ras # , ca s# multiplexing style. a ccesses begin with the registration of a bank activate command, and then it is followed by a read or write command. read and write accesses to the ddr2 sdram are 4 or 8-bit burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard drams. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. a sequential and gapless data rate is possible depending on burst length, cas latency, and speed grade of the device. table 1. ordering information part number clock frequency data rate power supply package AS4C32M16D2A-25BCN 400mhz 800mbps/pin v dd 1.8v, v ddq 1.8v fbga AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice rev. 1.4 1 jun. /2014
table 2. speed grade information speed grade clock frequency cas latency t rcd (ns) t rp (ns) AS4C32M16D2A-25BCN 400mhz 5 12.5 12.5 figure 1. ball assignment (fbga top view) a b c d e 123 789 vdd nc dq14 vssq vddq dq9 dq12 vssq vdd nc vss udm vddq dq11 vss . vssq udqs# udqs vssq vddq dq8 dq10 vssq vssq ldqs# vddq dq15 vddq dq13 vddq f dq6 vssq ldm ldqs vssq dq7 g vddq dq1 vddq vddq dq0 vddq h dq4 vssq dq3 dq2 vssq dq5 j vddl vref vss vssdl ck vdd k cke we# ras# ck# odt l nc ba0 ba1 cas# cs# m a10 a1 a2 a0 vdd n vss a3 a5 a6 a4 p a7 a9 a11 a8 vss r vdd a12 nc nc nc AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice rev. 1.4 2 jun. /2014
figure 2. block diagram ck# cke cs# ras# cas# we# dll clock buffer command decoder column counter control signal generator address buffer refresh counter 8m x 16 cell array (bank #0) row decoder 8m x 16 cell array (bank #1) row decoder 8m x 16 cell array (bank #2) row decoder 8m x 16 cell array (bank #3) row decoder column decoder column decoder column decoder column decoder mode register a10/ap a9 a11 a12 ba0 ba1 a0 ck data strobe buffer ldqs ldqs# udqs udqs# dq buffer ldm udm dq15 dq0 ~ odt ~ AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 3 jun. /2014
figure 3. state diagram (e)mrs setting mr, emr(1) emr(2) emr(3) ocd calibration initialization sequence idle all banks precharged self refreshing refreshing precharge power down activating active power down bank active writing writing with autoprecharge precharging reading with autoprecharge reading act c k e l c k e h ck e l w r rd a r d a w ra w r a wr rd r d pr, pra pr, pra pr, pra rda wra c k e l c k e h c k e l s r f c k e h ref ckel wr rd pr ckel ckel automatic sequence cammand sequence ckel = cke low, enter power down ckeh = cke high, exit power down,exit self refresh act = activate wr(a) = write (with autoprecharge) rd(a) = read (with autoprecharge) pr(a) = precharge (all) (e)mrs = (extended) mode register set srf = enter self refresh ref = refresh note: use caution with this diagram. it is indented to provide a floorplan of the possible state transitions and the commands to control them, not all details. in particular situations involving more than one bank, enabling/disabling on-die termination, power down entry/exit, timing restrictions during state transitions, among other things, are not captured in full detail. AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 4 jun. /2014
ball descriptions table 3. ball descriptions symbol type description ck, ck# input differential clock: ck, ck# are driven by the system clock. all sdram input signals are sampled on the crossing of positive edge of ck and negative edge of ck#. output (read) data is referenced to the crossings of ck and ck# (both directions of crossing). cke input clock enable: cke activates (high) and deactivates (low) the ck signal. if cke goes low synchronously with clock, the in ternal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. ba0, ba1 input bank address: ba0 and ba1 define to which bank t he bankactivate, read, write, or bankprecharge command is being applied. a0-a12 input address inputs: a0-a12 are sampled during the bankactivate command (row address a0-a12) and read/write command (col umn address a0-a9 with a10 defining auto precharge). cs# input chip select: cs# enables (sampled low) and di sables (sampled high) the command decoder. all commands are masked when cs# is sampled high. cs# provides for external bank selection on syst ems with multiple banks. it is considered part of the command code. ras# input row address strobe: the ras# signal defines the operation commands in conjunction with the cas# and we# signals and is latched at the crossing of positive edges of ck and negative edge of ck#. w hen ras# and cs# are asserted "low" and cas# is asserted "high," either t he bankactivate command or the precharge command is selected by the we# signal. when the we# is asserted "high," the bankactivate command is selected and the bank designated by ba is turned on to the active state. when the we# is asserted "low," the precharge command is selected and the bank designated by ba is switched to the idle state after the precharge operation. cas# input column address strobe: the cas# signal defines the operation commands in conjunction with the ras# and we# signals and is latched at the crossing of positive edges of ck and negative edge of ck#. w hen ras# is held "high" and cs# is asserted "low," the column access is star ted by asserting cas# "low." then, the read or write command is selected by asserting we# ?high " or ?low". we# input write enable: the we# signal defines the operati on commands in conjunction with the ras# and cas# signals and is latched at the crossing of positive edges of ck and negative edge of ck#. the we# input is used to select the bankactivate or precharge command and read or write command. ldqs, ldqs# udqs udqs# input / output bidirectional data strobe: specifies timing for input and output data. read data strobe is edge triggered. write data strobe provides a setup and hold time for data and dqm. ldqs is for dq0~7, udqs is for dq8~15. the data strobes ldos and udqs may be used in single ended mode or paired with ldqs# and udqs# to provide differential pair signaling to the sy stem during both reads and writes.a control bit at emr (1)[a10] enables or disables all complementary data strobe signals. ldm, udm input data input mask: input data is masked when dm is sampled high during a write cycle. ldm masks dq0-dq7, udm masks dq8-dq15. dq0 - dq15 input / output data i/o: bi-directional data bus. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. r eserves the r ight to change products or specification without notice rev. 1.4 5 jun. /2014
odt input on die termination: odt enables internal termination resistance. it is applied to each dq, ldqs/ldqs#, udqs/udqs#, ldm, and udm signal. the odt pin is ignored if the emr (1) is programmed to disable odt. v dd supply power supply: +1.8v 0.1v v ss supply ground v ddl supply dll power supply: +1.8v 0.1v v ssdl supply dll ground v ddq supply dq power: +1.8v 0.1v. v ssq supply dq ground v ref supply reference voltage for inputs: +0.5*v ddq nc - no connect: these pins should be left unconnected. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 6 jun. /2014
operation mode table 4 shows the truth table for the operation commands. table 4. truth table (note (1), (2)) command state cke n-1 cke n dm ba 0,1 a 10 a 0-9, 11-12 cs# ras# cas# we# bankactivate idle (3) h h x v row address l l h h single bank precharge any h h x v l x l l h l all banks precharge any h h x x h x l l h l write active (3) h h x v l column address (a0 ? a9) l h l l write with autoprecharge active (3) h h x v h l h l l read active (3) h h x v l column address (a0 ? a9) l h l h read and autoprecharge active (3) h h x v h l h l h extended mode register set idle h h x v op code l l l l no-operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x refresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x l h h h power down mode entry idle h l x x x x h x x x l h h h power down mode exit any l h x x x x h x x x l h h h data input mask disable active h x l x x x x x x x data input mask enable(5) active h x h x x x x x x x note 1: v=valid data, x=don't care, l=low level, h=high level note 2: cken signal is input level when commands are provided. note 3: cken -1 signal is input level one clock cycle before the commands are provided. note 4: these are states of bank designated by ba signal. note 5: device state is 4, and 8 burst operation. note 6: ldm and udm can be enabled respectively. AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 7 jun. /2014
functional description read and write accesses to the ddr2 sdram are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a progr ammed sequence. accesses begin wi th the registration of an active command, which is then followed by a read or wri te command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determi ne if the auto precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initializ ed. the following sections provide detailed information covering device initialization, register defin ition, command descriptions, and device operation. z power-up and initialization ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2*v ddq and odt *1 at a low state (all other inputs may be undefined.) the v dd voltage ramp time must be no greater than 200ms from when v dd ramps from 300mv to v dd min; and during the v dd voltage ramp, |v dd -v ddq ]7 - v dd , v ddl and v ddq are driven from a single power converter output, and - v tt is limited to 0.95 v max, and - v ref tracks v ddq /2. or - apply v dd before or at the same time as v ddl . - apply v ddl before or at the same time as v ddq . - apply v ddq before or at the same time as v tt & v ref . at least one of these two sets of conditions must be met. 2. start clock and maintain stable condition. 3. for the minimum of 200 s after stable power and clock (ck, ck#), then apply nop or deselect and take cke high. 4. wait minimum of 400ns then issue precharge all command. nop or deselect applied during 400ns period. 5. issue emrs(2) command. (to issue emrs (2) co mmand, provide ?low? to ba0, ?high? to ba1.) 6. issue emrs (3) command. (to issue emrs (3) command, provide ?high? to ba0 and ba1.) 7. issue emrs to enable dll. (to issue "dll enable" command, provide "low" to a0, "high" to ba0 and "low" to ba1.) 8. issue a mode register set command for ?dll reset?. (to issue dll reset command, provide "high" to a8 and "low" to ba0-1) 9. issue precharge all command. 10. issue 2 or more auto-refresh commands. 11. issue a mode register set command with low to a8 to initialize device operation. (i.e. to program operating parameters without resetting the dll.) 12. at least 200 clocks after step 8, execute ocd calibration (off chip driver impedance adjustment).if ocd calibration is not used, emrs ocd default command (a9=a8=a7=high) followed by emrs ocd calibration mo de exit command (a9=a8=a7=low) must be issued with other operating parameters of emrs. 13. the ddr2 sdram is now ready for normal operation. note 1: to guarantee odt off, v ref must be valid and a low level must be applied to the odt pin. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 8 jun. /2014
z mode register set (mrs) the mode register stores the data fo r controlling the various operating modes of ddr2 sdram. it controls cas latency, burst length, burst sequence, test mode, dll reset, wr, and various vendor specific options to make ddr2 sdram useful for various applications.the default va lue of the mode register is not defined, therefore the mode register must be programmed during initialization for proper operation. the mode register is written by asserting low on cs#, ras#, cas#, we#, ba0 and ba1, wh ile controlling the state of address pins a0 - a12. the ddr2 sdram should be in all bank precharge state with cke already high prior to writing into the mode register.the mode register set command cycle time (t mrd ) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all bank are in the precharge state.the mode register is divided into various fields depending on functionality. - burst length field (a2, a1, a0) this field specifies the data length of column access and selects the burst length. - addressing mode select field (a3) the addressing mode can be interleave mode or s equential mode. both sequential mode and interleave mode support burst length of 4 and 8. -cas latency field (a6, a5, a4) this field specifies the number of clock cycles from the assertion of the read command to the first read data. the minimum whole value of cas latency depends on the frequency of ck. the minimum whole value satisfying the following formula must be programmed into this field. t cac (min) Q cas latency x t ck - test mode field: a7; dll reset mode field: a8 these two bits must be programmed to "00" in normal operation. - (ba0, ba1): bank addresses to define mrs selection. table 5. mode register bitmap ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 0 pd wr dll tm cas latency bt burst length mode register a8 dll reset a7 mode a3 burst type a2 a1 a0 bl 0 no 0 normal 0 sequential 0 1 0 4 1 yes 1 test 1 interleave 0 1 1 8 note 1: .for ddr2-667/800/1066, wr (write recovery for autoprecharge) min is determined by t ck (avg) max and wr max is determined by t ck (avg) min. wr [cycles] = ru {t wr [ns]/t ck (avg)[ns]}, where ru stands fo r round up. the mode register must be programmed to this value.this is also used with t rp to determine t dal . a12 active power down exit time write recovery for autoprecharge *1 0 fast exit (use t xard ) a11 a10 a9 wr(cycles) a6 a5 a4 cas latency 1 slow exit (use t xards ) 0 0 0 reserved 0 0 0 reserved 0 0 1 2 0 0 1 reserved ba1 ba0 mrs mode 0 1 0 3 0 1 0 reserved 0 0 mr 0 1 1 4 0 1 1 3 0 1 emr(1) 1 0 0 5 1 0 0 4 1 0 emr(2) 1 0 1 6 1 0 1 5 1 1 emr(3) 1 1 0 7 1 1 0 6 1 1 1 8 1 1 1 7 AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 9 jun. /2014
z extended mode register set (emrs) - emr(1) the extended mode register(1) stores the data for enabling or disabling the dll, output driver strength, odt value selection and additive latency. the default value of the extended mode register is not defined, therefore the extended mode register must be wr itten after power-up for proper operat ion. the extended mode register is written by asserting low on cs#, ras#, cas#, we#, ba1 and high on ba0, while controlling the states of address pins a0 ~ a12. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. t he mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the extended mode regi ster. mode register contents can be changed using the same command and clock cycle requirements during nor mal operation as long as all banks are in the precharge state. a0 is used for dll enable or disable. a1 is used for enabling a half strength data-output driver. a3~a5 determine the additive latency, a2 and a6 are us ed for odt value selection, a7~a9 are used for ocd control, a10 is used for dqs# disable. - dll enable/disable the dll must be enabled for normal operation. dll enabl e is required during power up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of se lf refresh operation. any time the dll is enabled (and subsequently reset), 200 clock cycl es must occur before a read command can be issued to allow time for the internal clock to be synchronized wi th the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck parameters. table 6. extended mode register emr (1) bitmap ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 qoff 0 dqs# ocd program rtt additive latency rtt d.i.c dll extended mode register ba1 ba0 mrs mode a6 a2 rtt (nominal) 0 0 mr 0 0 odt disable a0 dll enable 0 1 emr(1) 0 1 75 0 enable 1 0 emr(2) 1 0 150 1 disable 1 1 emr(3) 1 1 50 a9 a8 a7 ocd calibration program a1 output driver impedance control driver size 0 0 0 ocd calibration mode exit; maintain setting 0 0 1 drive(1) 0 full strength 100% 0 1 0 drive(0) 1 reduced strength 60% 1 0 0 adjust mode *1 1 1 1 ocd calibration default *2 a5 a4 a3 additive latency 0 0 0 0 a12 qoff *3 0 0 1 1 0 output buffer enabled 0 1 0 2 a10 dqs# 1 output buffer disabled 0 1 1 3 0 enable 1 0 0 4 1 disable 1 0 1 5 1 1 0 6 1 1 1 reserved AS4C32M16D2A-25BCN no te 1: when adjust mode is issued, al from previously s et value must be applied. no te 2: after setting to default, ocd calibration mode needs to be exited by setting a9-a7 to 000. note 3: output disabled ? dqs, dqss, dqss #.this feature is intended to be used during i dd characterization of read current. alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a llianc e m em ory inc. r eser v es the r ight to change pr oduc ts or spec ification without notice rev. 1.4 10 jun. /2014
- emr(2) the extended mode register (2) controls refresh rela ted features. the default value of the extended mode register (2) is not defined, theref ore the extended mode register (2) must be written after power-up for proper operation. the extended mode register(2 ) is written by asserting low on cs#, ras#, cas#, we#, high on ba1 and low on ba0, while controlling the states of addr ess pins a0 ~ a12. the ddr2 sdram should be in all bank precharge with cke already high prior to wr iting into the extended mode register (2). the mode register set command cycle time (t mrd ) must be satisfied to complete t he write operation to the extended mode register (2). mode register c ontents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. table 7. extended mode register emr (2) bitmap ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 1 0 0 *1 srf 0 *1 dcc *4 pasr *3 extended mode register(2) a7 high temperature self-refresh rate enable 0 disable 1 enable *2 ba1 ba0 mrs mode a3 dcc enable *4 0 0 mr 0 disable 0 1 emr(1) 1 enable 1 0 emr(2) 1 1 emr(3) a2 a1 a0 partial array self refresh for 4 banks 000 full array 001 half array (ba[1:0]=00&01) 010 quarter array (ba[1:0]=00) 011 not defined 100 3/4 array (ba[1:0]=01,10&11) 101 half array (ba[1:0]=10&11) 110 quarter array (ba[1:0]=11) 111 not defined note 1: the rest bits in emrs(2) are reserved for future use and all bits in emrs(2) except a0-a2, a7, ba0 and ba1 must be programmed to 0 when setting the extended mode register(2) during initialization. note 2: due to the migration nature, user needs to ensure the dra m part supports higher than 85 tcase temperature self-refresh entry. if the high temperatur e self-refresh mode is suppor ted then controller can set the emrs2[a7] bit to enable the self-refresh rate in case of higher than 85 temperature self-refresh operation. note 3: if pasr (partial array self refresh) is enabled, data loca ted in areas of the array bey ond the specified location will be lost if self refresh is entered. data integrit y will be maintained if t ref conditions are met and no self refresh command is issued. note 4: dcc (duty cycle corrector) implemented, user may be giv en the controllability of dcc thru emr (2) [a3] bit. alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc . r eserves the r ight to change products or specification without notice AS4C32M16D2A-25BCN rev. 1.4 11 jun. /2014
- emr(3) no function is defined in extended mode register(3).the default value of the extended mode register(3) is not defined, therefore the extended mode r egister(3) must be programmed during initialization for proper operation. table 8. extended mode register emr (3) bitmap ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 1 1 0 *1 extended mode register(3) note 1: all bits in emr (3) except ba0 and ba1 are reserved for future use and must be set to 0 when programming the emr (3). AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. r eserves the r ight to change products or specification without notice rev. 1.4 12 jun. /2014
z off-chip drive (ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the following flow chart is an example of sequence.every calibration mode command should be followed by ?ocd ca libration mode exit? before any other command being issued.all mr should be programmed before entering o cd impedance adjustment and odt (on die termination) should be carefully controlled depending on system environment. figure 4. ocd impedance adjustment sequence start emrs:ocd calibration mode exit emrs:drive(1) dq &dqs high;dqs# low test emrs:ocd calibration mode exit emrs:enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs:ocd calibration mode exit emrs:drive(0) dq &dqs low;dqs# high test emrs:ocd calibration mode exit emrs:enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs:ocd calibration mode exit end emrs:ocd calibration mode exit all ok before entering ocd impedance adjustme nt, all mr should be programmed and odt should be carefully controlle d depending on system environment all ok AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 13 jun. /2014
- extended mode register for ocd impedance adjustment ocd impedance adjustment can be done using the followi ng emrs mode. in drive mode all outputs are driven out by ddr2 sdram. in driv e (1) mode, all dq, dqs signals are driven high and all dqs# signals are driven low. in drive (0) mode, all dq, dqs signals ar e driven low and all dqs# signals are drive high. in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibration default, output driver characteristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. output driver characteristics for ocd calib ration default are specified in the following table. ocd applies only to normal full strength output drive setting defined by emrs and if half strength is set, ocd default driver characteristics are not applicable. when ocd ca libration adjust mode is used, ocd default output driver characteristics are not applicable. after ocd calibration is completed or driver strength is set to default, subsequent emrs commands not intended to adjust ocd charac teristics must specify a7~a9 as ?000? in order to maintain the default or calibrated value. table 9.ocd drive mode program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive(1) dq, dqs, high and dqs# low 0 1 0 drive(0) dq, dqs, low and dqs# high 1 0 0 adjust mode 1 1 1 ocd calibration default - ocd impedance adjust to adjust output driver impedance, controllers must issue the adjust emrs command along with a 4bit burst code to ddr2 sdram as in the following table. for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must dr ive this burst code to all dqs at the same time. d t0 in the following table means all dq bits at bit time 0, d t1 at bit time 1, and so forth. the driver output impedance is adjusted for all ddr2 sdram dqs simultaneous ly and after ocd calibration, all dqs of a given ddr2 sdram will be adjusted to the same driver strength setting. the maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. the default setting maybe any step within the 16 step range. when adjust mode command is issued, al from previously set value must be applied. table 10.ocd adjust mode program 4bit burst code inputs to all dqs operation d t0 d t1 d t2 d t3 pull-up driver strength pull-down driver strength 0 0 0 0 nop nop 0 0 0 1 increase by 1 step nop 0 0 1 0 decrease by 1 step nop 0 1 0 0 nop increase by 1 step 1 0 0 0 nop decrease by 1 step 0 1 0 1 increase by 1 step increase by 1 step 0 1 1 0 decrease by 1 step increase by 1 step 1 0 0 1 increase by 1 step decrease by 1 step 1 0 1 0 decrease by 1 step decrease by 1 step other combinations reserved AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 14 jun. /2014
z odt (on die termination) on die termination (odt) is a feature that allows a dram to turn on/off termination resistance for each dq, udqs/udqs#, ldqs/ldqs#, udm, and ldm signal via the od t control pin. the odt feature is designed to improve signal integrity of the me mory channel by allowing the dram c ontroller to independently turn on/off termination resistance for any or all dram devices. the odt function is supported for active and stand by modes. it is turned off and not supported in self refresh mode. figure 5. functional representation of odt sw1 rval1 v ddq sw1 rval1 v ssq sw3 rval3 v ddq sw3 rval3 v ssq sw2 rval2 v ddq sw2 rval2 v ssq input pin dram input buffer switch (sw1, sw2, sw3) is enabled by odt pin. selection among sw1, sw2, and sw3 is determined by ?rtt (nominal)? in emr. termination included on all dqs, dm, dqs, and dqs# pins table 11.odt dc electrical characteristics parameter/condition symbol min. nom. max. unit note rtt effective impedance value for emrs(a6,a2)=0,1;75 ? rtt1(eff) 60 75 90 ? 1 rtt effective impedance value for emrs(a6,a2)=1,0;150 ? rtt2(eff) 120 150 180 ? 1 rtt effective impedance value for emrs(a6,a2)=1,1;50 ? rtt3(eff) 40 50 60 ? 1 rtt mismatch tolerance between any pull-up/pull-down pair rtt(mis) -6 - 6 2 note 1: measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin seperately, then measure current i(v ih (ac)) and i(v il (ac)) respectively. () () ? ih il ih il vac vac rtt(eff)= i(v (ac))-i(v (ac)) note 2: measurement defintion for rtt (mis): measure voltage (vm) at test pin (midpoint) with no load. 1 100% ?? ? ?? ?? ddq 2xvm rtt(mis)= v AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 15 jun. /2014
z bank activate command the bank activate command is issued by holding cas# and we# high with cs# and ras# low at the rising edge of the clock. the bank addresses ba0 and ba1 are us ed to select the desired bank. the row addresses a0 through a12 are used to determine which row to activate in the selected bank. the bank activate command must be applied before any read or write operation can be execut ed. immediately after the bank active command, the ddr2 sdram can accept a read or write command (with or without auto-precharge) on the following clock cycle. if a r/w command is issued to a bank that has not satisfied the t rcd min specification, then additive latency must be programmed into the device to delay the r/w command wh ich is internally issued to the device. the additive latency value must be chosen to assure t rcd min is satisfied. additive latencies of 0, 1, 2, 3, 4, and 5 are supported. once a bank has been activated it must be precharged bef ore another bank activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , respectively. the minimum time interval between successive bank activate commands to the same bank is determined (t rc ). the minimum time interval between bank active commands is t rrd z read and write access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting ras# high, cs# and cas# low at the clock? s rising edge. we# must also be defined at this time to determine whether the access cycle is a read operation (we# high) or a write operation (we # low). the ddr2 sdram provides a fast column access operation. a single read or write command will initiate a serial read or write operation on successive clock cycles. the boundary of the burst cycle is stri ctly restricted to specific segments of the page length. any system or application incorporating r andom access memory products should be properly designed, tested, and qualified to ensure proper use or access of such memory products. disproportionate, excessive, and/or repeated access to a particular address or addr esses may result in reduction of product life. z posted cas# posted cas# operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a cas# read or write command to be issued immediately after the ras bank activate command (or any time during the ras# -cas#-delay time, t rcd , period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of al and the cas latenc y (cl). therefore if a user chooses to issue a r/w command before the t rcd min, then al (greater than 0) must be writt en into the emr(1). the write latency (wl) is always defined as rl - 1 (read latency -1) where read lat ency is defined as the sum of additive latency plus cas latency (rl=al+cl). read or write operations using al allow seamless bursts (refer to seamless operation timing diagram examples in read burst and write burst section) z burst mode operation burst mode operation is used to provide a constant flow of data to memory loca tions (write cycle), or from memory locations (read cycle). the parameters that define how the burst mode w ill operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst m odes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and defined by the addresses a0 ~ a2 of the mrs. the burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (a3) of the mrs. seamless burst read or write operations are supported. interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. for burst interruption of a read or write burst when burst length = 8 is used, see the ?burst interruption? section of this datasheet. a burst stop command is not supported on ddr2 sdram devices. AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 16 jun. /2014
table 12.burst definition, addressing seque nce of sequential and interleave mode burst length start address sequential interleave a2 a1 a0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 z burst read command the burst read command is initiated by having cs# and cas# low while holding ras# and we# high at the rising edge of the clock. the addr ess inputs determine the starting colu mn address for the burst. the delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data str obe output (dqs) is driven low 1 clo ck cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is sy nchronized with the rising edge of the data strobe (dqs). each subsequent data-out appears on the dq pin in phas e with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) pl us cas latency (cl). the cl is defined by the mode register set (mrs), similar to the existing sdr and ddr sdrams. the al is defined by the extended mode register set (1) (emrs (1)). ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the emrs ?enable dqs? mode bit; timing advant ages of differential mode are realized in system design. the method by which t he ddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs#. this distinction in timing methods is guarant eed by design and characterization. note that when differential data strobe mode is disabled via the emrs, t he complementary pin, dqs#, must be tied externally to v ss through a 20 ? to 10 k? resistor to insure proper operation. z burst write operation the burst write command is initiated by having cs#, cas# and we# low while holding ras# high at the rising edge of the clock. the address inputs determine the starting column address. write latency (wl) is defined by a read latency (rl) minus one and is equal to (al + cl -1);and is the num ber of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first dqs strobe. a data strobe signal (dqs) s hould be driven low (preamble) one clock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the t dqss specification must be satisfied for each positiv e dqs transition to its associated clock edge during write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed, which is 4 or 8 bit burst. when the burst has finis hed, any additional data supplied to the dq pins will be ignored. the dq signal is ignored after the burst write oper ation is complete. the time from the completion of the burst write to bank precharge is the write recovery time (wr). ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the emrs ?enable dqs? mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured re lative to the rising or falling edges of dqs crossing at the specified ac/dc levels. in differential mode, t hese timing relationships are measured relative to the crosspoint of dqs and its complement, dqs#. this di stinction in timing methods is guaranteed by design and characterization. note that when differential data st robe mode is disabled via the emrs, the complementary pin, dqs#, must be tied externally to v ss through a 20 ? to 10k? resistor to insure proper operation. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 17 jun. /2014
z write data mask one write data mask (dm) pin for each 8 data bits (d q) will be supported on ddr2 sdrams, consistent with the implementation on ddr sdrams. it has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identic ally to data bits to insure matched system timing. dm is not used during read cycles. z precharge operation the precharge command is used to precharge or clos e a bank that has been activated. the precharge command is triggered when cs#, ras# and we# are low and cas# is high at the rising edge of the clock. the precharge command can be used to precharge each bank independently or all banks simultaneously. three address bits a10, ba1, and ba0 are used to define which bank to precharge when the command is issued. table 13.bank selection for precharge by address bits a10 ba1 ba0 precharged bank(s) low low low bank 0 only low low high bank 1 only low high low bank 2 only low high high bank 3 only high don?t care don?t care all banks z burst read operation followed by precharge minimum read to precharge command spacing to the same bank = al + bl/2 + max (rtp, 2) - 2 clocks. for the earliest possible precharge, the precharge comm and may be issued on the rising edge which ?additive latency (al) + bl/2 clocks? after a read command. a new bank active (command) may be issued to the same bank after the ras# precharge time (t rp ). a precharge command cannot be issued until t ras is satisfied. the minimum read to precharge spacing has also to sa tisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a read to precharge command. this time is called t rtp (read to precharge). for bl = 4 this is the time from the actual read (al after the read command) to precharge command. for bl = 8 this is the time from al + 2 clocks after the read to the precharge command. z burst write operation followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + t wr . for write cycles, a delay must be satisfied from the completion of the last bur st write cycle until the pr echarge command can be issued. this delay is known as a write recovery time (t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay, as ddr2 sdram does not support any burst interrupt by a precharge command. t wr is an analog timing parameter and is not the programmed value for t wr in the mrs. z auto precharge operation before a new row in an active bank can be opened, t he active bank must be precharged using either the precharge command or the auto-precharge function. when a read or a write command is given to the ddr2 sdram, the cas# timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the ear liest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto-precharge functi on is engaged. during auto-precharge, a read command will execute as normal with the exc eption that the active bank will begin to precharge on the rising edge which is cas latency (cl) clock cycles before the end of the read burst. auto-precharge also be implemented during write commands. the precharge operation engaged by t he auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. this feature allows the precharge operation to be partially or completely hidden duri ng burst read cycles (dependent upon cas latency) thus improving system performance for r andom data access. the ras# lockout circuit internally delays the precharge operation until the array restore operation has been completed (t ras satisfied) so that the auto precharge command may be issued with any read or write command. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 18 jun. /2014
z burst read with auto precharge if a10 is high when a read command is issued, t he read with auto-precharge function is engaged. the ddr2 sdram starts an auto-precharge operation on the rising edge which is (a l + bl/2) cycles later from the read with ap command if t ras (min) and t rtp are satisfied. if t ras (min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, the start point of auto-prec harge operation will be delayed until t rtp (min) is satisfied. in case the internal precharge is pushed out by t rtp , t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto-precharge to the next activate command becomes al + t rtp + t rp . for bl = 8 the time from read with auto-precharge to the next activate command is al + 2 + t rtp + t rp . note that both parameters t rtp and t rp have to be rounded up to the next integer value. in any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. a new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) the ras# precharge time (t rp ) has been satisfied from the clock at which the auto-precharge begins. (2) the ras# cycle time (t rc ) from the previous bank activation has been satisfied. z burst write with auto precharge if a10 is high when a write command is issued, t he write with auto-precharge function is engaged. the ddr2 sdram automatically begins precharge operation after the completion of the burst write plus write recovery time (t wr ). the bank undergoing auto-precharge from t he completion of the write burst may be reactivated if the following two conditions are satisfied. (1) the data-in to bank activate delay time (wr + t rp ) has been satisfied. (2) the ras# cycle time (t rc ) from the previous bank activation has been satisfied. table 14.precharge & auto precharge clariification from command to command minimum delay between from command to to command unit notes read precharge (to same bank as read) al+bl/2+max(rtp,2)-2 t ck 1,2 precharge all al+bl/2+max(rtp,2)-2 read w/ap precharge (to same bank as read w/ap) al+bl/2+max(rtp,2)-2 t ck 1,2 precharge all al+bl/2+max(rtp,2)-2 write precharge (to same bank as write) wl+bl/2+t wr t ck 2 precharge all wl+bl/2+t wr write w/ap precharge (to same bank as write w/ap) wl+bl/2+t wr t ck 2 precharge all wl+bl/2+t wr precharge precharge (to same bank as precharge) 1 t ck 2 precharge all 1 precharge all precharge 1 t ck 2 precharge all 1 note 1: rtp [cycles] =ru {t rtp [ns]/t ck (avg) [ns]}, where ru stands for round up. note 2: for a given bank, the precharge period should be c ounted from the latest precharge command, either one bank precharge or precharge all, issued to that bank.the prechrage period is satisfied after t rp or t rp all(=t rp for 4 bank device) depending on the latest precharge command issued to that bank. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 19 jun. /2014
z refresh command when cs#, ras# and cas# are held low and we# high at the rising edge of the clo ck, the chip enters the refresh mode (ref). all banks of the ddr2 sdram must be precharged and idle for a minimum of the precharge time (t rp ) before the refresh command (ref) can be applied. an address counter, internal to the device, supplies the bank address during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of t he ddr2 sdram will be in the precharged (idle) state. a delay between the refresh command (ref) and the nex t activate command or subsequent refresh command must be greater than or equal to the refresh cycle time (t rfc ).to allow for improved efficiency in scheduling and switching between tasks, some flexibilit y in the absolute refresh interval is provided. a maximum of eight refresh commands can be posted to any given ddr2 s dram, meaning that the maximum absolute interval between any refresh command and the next refresh command is 9 * t refi . z self refresh operation the self refresh command can be used to retain data in the ddr2 sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr2 sdram retains data without external clocking. the ddr2 sdram device has a built-in timer to accommodate self refresh operation. the self refresh command is defined by having cs#, ras#, cas# and cke# held lo w with we# high at the rising edge of the clock. odt must be turned off before issuing self refresh comm and, by either driving odt pin low or using emrs command. once the command is registered, cke must be held low to keep the device in self refresh mode. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self refresh mode all of the external signals except cke, are ?don?t care?. for proper self refres h operation all power supply pins (v dd , v ddq , v ddl and v ref ) must be at valid levels. the dram initiates a minimum of one refresh command internally within t cke period once it enters self refresh mode. the clock is internally disabled during se lf refresh operation to save power. the minimum time that the ddr2 sdram must remain in self refresh mode is t cke . the user may change the external clock frequency or halt the external clock one clock after self refresh entry is registered, however, the clock must be restarted and stable before the device can exit self refresh operation. the procedure for exiting self refresh requires a sequenc e of commands. first, the clock must be stable prior to cke going back high. once self refresh ex it is registered, a delay of at least t xsnr must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the entire self refresh exit period t xsrd for proper operation except for self refresh re-entry. upon exit from self refresh, the ddr2 sdram can be put back into self refresh mode after waiting at least t xsnr period and issuing one refresh command(refresh period of t rfc ). nop or deselect commands must be registered on each positive clock edge during the self refresh exit interval t xsnr . odt should be turned off during t xsrd . the use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. u pon exit from self refresh, the ddr2 sdram requires a minimum of one extra auto refresh command before it is put back into self refresh mode. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 20 jun. /2014
z power-down power-down is synchronously entered w hen cke is registered low along with nop or deselect command. no read or write operation may be in progress when cke goes low. these operations are any of the following: read burst or write burst and recovery. cke is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, mode register or extended mode register command time, or autorefresh is in progress. the dll should be in a locked state when power-down is entered. otherwise dll should be reset after exiting power-down mode for proper read operation. if power-down occurs when all banks are precharged, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank , this mode is referred to as active power-down. for active power-down two different power saving modes can be selected within the mrs register, address bit a12. when a12 is set to ?low? this mode is referred as ?standard active power-down mode? and a fast power-down exit timing defined by the t xard timing parameter can be used. when a12 is set to ?high? this mode is referred as a power saving ?low power active power-down mode?. this mode takes longer to exit from the power-down mode and the t xards timing parameter has to be satisfied. entering power-down deactivates the input and output buffers, excluding ck, ck#, odt and cke. also the dll is disabled upon entering precharge power- down or slow exit active power-down, but the dll is kept enabled during fast exit active power-down. in power- down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are ?don?t care?. po wer-down duration is limited by 9 times t refi of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid, executable command can be app lied with power-down exit latency, t xp , t xard or t xards , after cke goes high. power-down exit latencies are defi ned in the ac spec table of this data sheet. z asynchronous cke low event dram requires cke to be maintained ?high? for all va lid operations as defined in this datasheet. if cke asynchronously drops ?low? during any valid peration dram is not guaranteed to preserve the contents of array. if this event occurs, memory controller must sati sfy dram timing specification td elay efore turning off the clocks. stable clocks must exist at the input of dram before cke is rais ed ?high? again. dram must be fully re-initialized. dram is ready for normal operation after the initialization sequence. z input clock frequency change during precharge power down ddr2 sdram input clock frequency can be changed under following condition: ddr2 sdram is in precharged power down mode. odt must be turned off and c ke must be at logic low level. a minimum of 2 clocks must be waited after cke goes low befor e clock frequency may change. sdram input clock frequency is allowed to change only within minimu m and maximum operating frequency specified for the particular speed grade. during input clock frequency change, odt and cke must be held at stable low levels. once input clock frequency is changed, stable new clo cks must be provided to dram before precharge power down may be exited and dll must be reset via emrs after precharge power down exit. depending on new clock frequency an additional mrs command may need to be issued to appropriately set the wr, cl etc. during dll re-lock period, odt must remain off. after the dll lock time, the dram is ready to operate with new clock frequency. z no operation command the no operation command should be used in cases when t he ddr2 sdram is in an idle or a wait state. the purpose of the no operation command (nop) is to pr event the ddr2 sdram from registering any unwanted commands between operations. a no operation command is registered when cs# is low with ras#, cas#, and we# held high at the rising edge of the clock. a no operation comm and will not terminate a previous operation that is still executing, such as a burst read or write cycle. z deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs# is brought high at the rising edge of the clock, the ras#, cas#, and we# signals become don?t cares. AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 21 jun. /2014
table 15. absolute maximum dc ratings symbol parameter values unit note v dd voltage on vdd pin relative to vss -1.0 ~ 2.3 v 1,3 v ddq voltage on vddq pin relative to vss -0.5 ~ 2.3 v 1,3 v ddl voltage on vddl pin relative to vss -0.5 ~ 2.3 v 1,3 v in , v out voltage on any pin relative to vss - 0.5 ~ 2.3 v 1,4 t stg storage temperature - 55~100 c1,2 note1: stress greater than those listed under ?absolute maximum ratings? may cause permanent damage to the devices. this is a stress rating only and functional operat ion of the device at thes e or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note2: storage temperature is the case temperature on the center/t op side of the dram. note3: when v dd and v ddq and v ddl are less than 500mv, vref may be equal to or less than 300mv. note4: voltage on any input or i/o may not exceed voltage on v ddq . table 16. operating temperature condition symbol parameter values unit note t oper normal operating temperature 0~85 c1 extended operating temperature 85~95 c1,2 note1: operating temperature is the case surf ace temperature on center/top of the dram. note2: if tc exceeds 85c, the dram must be refreshed externally at 2x refresh. it is required to set trefi=3.9s in auto refresh mode and to set ?1? for emrs (2) bit a7 in self refresh mode. table 17. recommended dc operat ing conditions (sstl_1.8) symbol parameter min. typ. max. unit note v dd power supply voltage 1.7 1.8 1.9 v 1 v ddl power supply voltage for dll 1.7 1.8 1.9 v 5 v ddq power supply voltage for i/o buffer 1.7 1.8 1.9 v 1,5 v ref input reference voltage 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq mv 2,3 v tt termination voltage v ref - 0.04 v ref v ref + 0.04 v 4 note1: there is no specific device vdd supply voltage r equirement for sstl_18 compliance. however under all conditions v ddq must be less than or equal to v dd. note2: the value of v ref may be selected by the user to provide optim um noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . note3: peak to peak ac noise on v ref may not exceed +/-2 % v ref (dc). note4: v tt of transmitting device must track v ref of receiving device. note5: v ddq tracks with v dd , v ddl tracks with v dd . ac parameters are measured with v dd , v ddq and v ddl tied together AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 22 jun. /2014
table 18. input logic level symbol parameter -18 -25/3 unit min. max. min. max. vih (dc) dc input logic high voltage v ref + 0.125 v ddq + 0.3 v ref + 0.125 v ddq + 0.3 v vil (dc) dc input low voltage - 0.3 v ref - 0.125 - 0.3 v ref - 0.125 v vih (ac) ac input high voltage v ref + 0.2 - v ref + 0.2 v ddq + v p eak v vil (ac) ac input low voltage - v ref - 0.2 v ssq - v p eak v ref - 0.2 v vid (ac) ac differential voltage 0.5 v ddq + 0.6 0.5 v ddq v vix (ac) ac differential crosspoint voltage 0.5 x v ddq - 0.175 0.5 x v ddq + 0.175 0.5 x v ddq - 0.175 0.5 x v ddq + 0.175 v note1: refer to overshoot/undershoot specification for v peak value: maximum peak amplitude allowed for overshoot and undershoot. table 19. ac input test conditions symbol parameter value unit note v ref input reference voltage 0.5 x v ddq v 1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew rate input signal minimum slew rate 1.0 v/ns 2, 3 note1: input waveform timing is referenced to the input signal crossing through the v ih / il (ac) level applied to the device under test. note2: the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges . note3: ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. table 20. differential ac output parameters symbol parameter value unit note min. max. v ox (ac) ac differential cross point voltage 0.5 x v ddq - 0.125 0.5 x v ddq + 0.125 v 1 note1: the typical value of v ox (ac) is expected to be about 0.5 x v ddq of the transmitting device and v ox (ac) is expected to track variations in v ddq . v ox (ac) indicates the voltage at wh ich differential output signals must cross. table 21. ac overshoot/undershoot specifi cation for address and control pins (a0-a12, ba0-ba1, cs#, ras#, cas#, we#, cke, odt) parameter -18 -25 -3 unit maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 v maximum peak amplitude allowed for undershoot area 0.5 0.5 0.5 v maximum overshoot area above v dd 0.5 0.66 0.8 v-ns maximum undershoot area below v ss 0.5 0.66 0.8 v-ns AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. r eserves the r ight to change products or specification without notice rev. 1.4 23 jun. /2014
table 22. ac overshoot/undershoot specification for clock, data, strobe, and mask pins (dq, udqs, ldqs, udqs#, ldqs#, dm, ck, ck#) parameter -18 -25 -3 unit maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 v maximum peak amplitude allowed for undershoot area 0.5 0.5 0.5 v maximum overshoot area above v dd 0.19 0.23 0.23 v-ns maximum undershoot area below v ss 0.19 0.23 0.23 v-ns table 23. output ac test conditions symbol parameter value unit note v otr output timing measurement reference level 0.5xv ddq v 1 note1: the v ddq of the device under test is referenced. table 24. output dc current drive symbol parameter value unit note i oh (dc) output minimum source dc current -13.4 ma 1, 3, 4 i ol (dc) output minimum sink dc current 13.4 ma 2, 3, 4 note1: v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq ) /i oh must be less than 21 ? for values of v out between v ddq and v ddq - 280 mv. note2: v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ? for values of v out between 0 v and 280 mv. note3: the dc value of v ref applied to the receiving device is set to v tt note4: the values of i oh (dc) and i ol (dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and vil max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating point (see jedec standard: section 3.3 of jesd8-15a) along a 21 ? load line to define a convenient driver current for measurement. table 25. capacitance (v dd = 1.8v, f = 1mhz, t oper = 25 c) symbol parameter value unit min. max. c in input capacitance : command and address 1.0 1.75 pf c ck input capacitance (ck, ck#) 1.0 2.0 pf c i/o dm, dq, dqs input/output capacitance 2.5 3.5 pf dc in delta input capacitance: command and address - 0.25 pf dc ck delta input capacitance: ck, ck# - 0.25 pf dc io delta input/output capacitance: dm, dq, dqs - 0.5 pf note: these parameters are periodically sampled and are not 100% tested. AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 24 jun. /2014
table 26. idd specification pa rameters and test conditions (v dd = 1.8v 0.1v, t oper = 0~85 c) parameter & test condition symbol -18 -25 -3 unit max. operating one bank active-precharge current: t ck =t ck (min), t rc = t rc (min), t ras = t ras (min); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd0 95 90 85 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (min), al = 0; t ck = t ck (min),t rc = t rc (min), t ras = t ras (min), t rcd = t rcd (min);cke is high, cs# is high between valid commands;address bus inputs are switching; data pattern is same as i dd4w i dd1 105 100 95 ma precharge power-down current: all banks idle;t ck =t ck (min); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd2p 8 8 8 ma precharge quiet standby current: all banks idle; t ck =t ck (min); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating i dd2q 40 35 35 ma precharge standby current: all banks idle; t ck = t ck (min); cke is high, cs# is high; other control and address bus inputs are switching; data bus inputs are switching i dd2n 45 40 40 ma active power-down current: all banks open; t ck =t ck (min); cke is low; other control and address bus inputs are stable; data bus inputs are floating mrs(a12)=0 i dd3p 30 30 30 ma mrs(a12)=1 15 15 15 ma active standby current: all banks open; t ck = t ck (min), t ras = t ras (max), t rp = t rp (min); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd3n 65 60 60 ma operating burst write current: all banks open,continuous burst writes; bl = 4, cl = cl (min), al = 0; t ck = t ck (min), t ras = t ras (max), t rp = t rp (min); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4w 175 135 125 ma operating burst read current: all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (min), al = 0; t ck = t ck (min), t ras = t ras (max), t rp = t rp (min); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4r 175 135 125 ma burst refresh current: t ck = t ck (min); refresh command at every t rfc (min) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd5 100 90 85 ma self refresh current: ck and ck# at 0v; cke 0.2v;other control and address bus inputs are floating; data bus inputs are floating i dd6 6 6 6 ma operating bank interleave read current: all bank interleaving reads, i out = 0ma; bl = 4, cl = cl (min), al =t rcd (min) - 1 x t ck (min); t ck = t ck (min), t rc = t rc (min), t rrd = t rrd (min), t rcd = t rcd (min); cke is high, cs# is high between valid commands; address bus inputs are stable dur ing deselects.data pattern is same as idd4r i dd7 220 180 160 ma AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 25 jun. /2014
table 27. electrical characteristics and recommended a.c. operating conditions (v dd = 1.8v 0.1v, t oper = 0~85 c) symbol parameter -18 -25 -3 unit specific notes min. max. min. max. min. max. t ck(avg) average clock period cl=3 - - 5 8 5 8 ns 15, 33, 34 cl=4 3.75 8 3.75 8 3.75 8 ns 15, 33, 34 cl=5 3 8 2.5 8 3 8 ns 15, 33, 34 cl=6 2.5 8 2.5 8 - - ns 15, 33, 34 cl=7 1.875 8 - - - - ns 15, 33, 34 t ch(avg) average clock high pulse width 0.48 0.52 0.48 0.52 0.48 0.52 t ck 34, 35 t cl(avg) average clock low pulse width 0.48 0.52 0.48 0.52 0.48 0.52 t ck 34, 35 wl write command to dqs associated clock edge rl-1 rl-1 rl-1 t ck t dqss dqs latching rising transitions to associated clock edges -0.25 0.25 -0.25 0.25 -0.25 0.25 t ck 28 t dss dqs falling edge to ck setup time 0.2 - 0.2 - 0.2 - t ck 28 t dsh dqs falling edge hold time from ck 0.2 - 0.2 - 0.2 - t ck t dqsh dqs input high pulse width 0.35 - 0.35 - 0.35 - t ck t dqsl dqs input low pulse width 0.35 - 0.35 - 0.35 - t ck t wpre write preamble 0.35 - 0.35 - 0.35 - t ck t wpst write postamble 0.4 0.6 0.4 0.6 0.4 0.6 t ck 10 t is(base) address and control input setup time 0.125 - 0.175 - 0.2 - ns 5, 7, 9, 22, 27 t ih(base) address and control input hold time 0.2 - 0.25 - 0.275 - ns 5, 7, 9, 23, 27 t ipw control & address input pulse width for each input 0.6 - 0.6 - 0.6 - t ck t ds(base ) dq & dm input setup time 0 - 0.05 - 0.1 - ns 6, 7, 8, 20, 26, 29 t dh(base ) dq & dm input hold time 0.075 - 0.125 - 0.175 - ns 6, 7, 8, 21, 26, 29 t dipw dq and dm input pulse width for each input 0.35 - 0.35 - 0.35 - t ck t ac dq output access time from ck, ck# -0.35 0.35 -0.4 0.4 -0.45 0.45 ns 38 t dqsck dqs output access time from ck, ck# -0.325 0.325 -0.35 0.35 -0.4 0.4 ns 38 t hz data-out high-impedance time from ck, ck# - t ac(max) - t ac(max) - t ac(max) ns 18, 38 t lz(dqs) dqs(dqs#) low-impedance time from ck, ck# t ac(min) t ac(max) t ac(min) t ac(max) t ac(min) t ac(max) ns 18, 38 t lz(dq) dq low-impedance time from ck, ck# 2t ac(min) t ac(max) 2t ac(min) t ac(max) 2t ac(min) t ac(max) ns 18, 38 t dqsq dqs-dq skew for dqs and associated dq signals - 0.175 - 0.2 - 0.24 ns 13 t hp ck half pulse width min(t cl ,t ch )- min(t cl ,t ch )- min(t cl ,t ch ) - ns 11, 12, 35 t qhs dq hold skew factor - 0.25 - 0.3 - 0.34 ns 12, 36 t qh dq/dqs output hold time from dqs t hp -t qhs - t hp -t qhs - t hp -t qhs - ns 37 t rpre read preamble 0.9 1.1 0.9 1.1 0.9 1.1 t ck 19, 39 t rpst read postamble 0.4 0.6 0.4 0.6 0.4 0.6 t ck 19, 40 t rrd active to active command period 10 - 10 - 10 - ns 4, 30 t ccd cas# to cas# command delay 2 - 2 - 2 - t ck t wr write recovery time 15 - 15 - 15 - ns 30 t dal auto power write recovery + precharge time wr + t rp - wr + t rp - wr + t rp - ns 14, 31 t wtr internal write to read command delay 7.5 - 7.5 - 7.5 - ns 3, 24, 30 AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 26 jun. /2014
t rtp internal read to precharge command delay 7.5 - 7.5 - 7.5 - ns 3, 30 t cke cke minimum pulse width 3 - 3 - 3 - t ck 25 t xsnr exit self refresh to non-read command delay t rfc +10 - t rfc +10 - t rfc +10 - ns 30 t xsrd exit self refresh to a read command 200 - 200 - 200 - t ck t xp exit precharge power down to any command 3 - 2 - 2 - t ck t xard exit active power down to read command 3 - 2 - 2 - t ck 1 t xards exit active power down to read command(slow exit, lower power) 10-al - 8-al - 7-al - t ck 1, 2 t aond odt turn-on delay 2 2 2 2 2 2 t ck 16 t aon odt turn-on t ac(min) t ac (max) +2.575 t ac(min) t ac (max) +0.7 t ac(min) t ac (max) +0.7 ns 6, 16, 38 t aonpd odt turn-on (power-down mode) t a c(min) +2 3 t ck +t a c(max) +1 t ac (min) +2 2 t ck +t a c(max) +1 t ac (min) +2 2 t ck +t ac (max) +1 ns t aofd odt turn-off delay 2.5 2.5 2.5 2.5 2.5 2.5 t ck 17, 42 t aof odt turn-off t ac(min) t ac(max) +0.6 t ac(min) t ac(max) +0.6 t ac(min) t ac(max) +0.6 ns 17, 41, 42 t aofpd odt turn-off (power-down mode) t ac (min) +2 2.5 t ck +t ac (max) +1 t ac (min) +2 2.5 t ck +t ac (max) +1 t a c(min) +2 2.5 t ck +t ac (max) +1 ns t anpd odt to power down entry latency 4 - 3 - 3 - t ck t axpd odt power down exit latency 11 - 8 - 8 - t ck t mrd mode register set command cycle time 2 - 2 - 2 - t ck t mod mrs command to odt update delay 0 12 0 12 0 12 ns 30 t oit ocd drive mode output delay 0 12 0 12 0 12 ns 30 t delay minimum time clocks remains on after cke asynchronously drops low t is + t ck +t ih - t is + t ck +t ih - t is + t ck +t ih - ns 15 t rfc refresh to active/refresh command time 105 - 105 - 105 - ns 43 t refi average periodic refesh interval @ 0 Q tc Q +85 - 7.8 - 7.8 - 7.8 s 43 @ +85 tc Q +95 - 3.9 - 3.9 - 3.9 s 43 t rcd ras# to cas# delay time 13.125 - 12.5 - 15 - ns t rp row precharge delay time 13.125 - 12.5 - 15 - ns t rc row cycle delay time 58.125 - 57.5 - 60 - ns t ras row active delay time 45 70k 45 70k 45 70k ns AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 27 jun. /2014
general notes, which may apply for all ac parameters: note 1: ddr2 sdram ac timing reference load the below figure represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system env ironment or a depiction of the actual load presented by a production tester. figure 6. ac timing reference load vddq dut dqs dqs# dq v tt =v ddq /2 25 ? timing reference point ouput the output timing reference voltage level for single ended si gnals is the crosspoint with vtt. the output timing reference voltage level for differential signals is the cro sspoint of the true (e.g. dqs) and the complement (e.g. dqs#) signal. note 2: slew rate measurement levels a) output slew rate for falling and rising edges is measured between v tt - 250 mv and v tt + 250 mv for single ended signals. for differential signals (e.g. dqs ? dqs#) output slew rate is measured between dqs ? dqs# = - 500 mv and dqs ? dqs# = + 500 mv. output slew ra te is guaranteed by design, but is not necessarily tested on each device. b) input slew rate for single ended signals is measured from v ref (dc) to v ih (ac), min for rising edges and from v ref (dc) to v il (ac),max for falling edges.for differential signals (e .g. ck ? ck#) slew rate for rising edges is measured from ck ? ck# = - 250 mv to ck -ck# = + 500 mv (+ 250 mv to - 500 mv for falling edges). c) v id is the magnitude of the difference between the i nput voltage on ck and the input voltage on ck#, or betweendqs and dqs# for differential strobe. note 3: ddr2 sdram output slew rate test load output slew rate is characterized under the test conditions as bellow figure 7. slew rate test load vddq dut dqs dqs# dq v tt =v ddq /2 25 ? test point ouput AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 28 jun. /2014
note 4: differential data strobe ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the emrs ?enable dqs? mode bit; timing advant ages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs#. this distinction in timing methods is guarant eed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs#, must be tied externally to v ss through a 20 ? to 10 k ? resistor to insure proper operation note 5: ac timings are for linear signal transitions. note 6: all voltages are referenced to v ss . note 7: these parameters guarantee device behav ior, but they are not necessa rily tested on each device.they may be guaranteed by device design or tester correlation. note 8: tests for ac timing, i dd , and electrical (ac and dc) characterist ics, may be conducted at nominal reference/supply voltage levels, but the related spec ifications and device operation are guaranteed for the full voltage range specified. specific notes for dedicated ac parameters note 1: user can choose which active power down exit timing to use via mrs (bit 12). t xard is expected to be used for fast active power down exit timing. t xards is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. note 2: al=additive latency. note 3: this is a minimum requirement. minimum read to precharge timing is al+bl/2 provided that the t rtp and t ras (min) have been satisfied. note 4: a minimum of two clocks (2* t ck ) is required irrespective of operating frequency. note 5: timings are specified with command/addr ess input slew rate of 1.0 v/ns. note 6: timings are specified with dqs, dm, and dqs?s (i n single ended mode) input slew rate of 1.0v/ns. note 7: timings are specified with ck/ck# differential sl ew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in di fferential strobe mode and a slew rate of 1 v/ns in single ended mode. note 8: data setup and hold time derating. for all input signals the total t ds (setup time) and t dh (hold time) required is calculated by adding the data sheet. t ds(base) and t dh(base) value to the ? t ds and ? t dh derating value respectively. example: t ds (total setup time) =t ds (base) + ? t ds .for slew rates in between the values listed in tables 28, the derating values may obtained by linear interpolation.thes e values are typically not subject to production test. they are verified by design and characterization. table 28. ddr2-667/800/1066 t ds /t dh derating with differential data strobe tds, tdh derating values for ddr2-667, ddr2-800, ddr2-1066 (all units in ps; the note applies to the entire table) dqs,dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h dq slew rate v/ns 2.0 100 45 100 45 100 45 - - - - - - - - - - - - 1.5 67 21 67 21 67 21 79 33 - - - - - - - - - - 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - 0.9 - - -5 -14 -5 -14 7 -2 19 10 31 22 - - - - - - 0.8 - - - - -13 -31 -1 -19 11 -7 23 5 35 17 - - - - 0.7 - - - - - - -10 -42 2 -30 14 -18 26 -6 38 6 - - 0.6 - - - - - - - - -10 -59 2 -47 14 -35 26 -23 38 -11 0.5 - - - - - - - - - - -24 -89 -12 -77 0 -65 12 -53 0.4 - - - - - - - - - - - - -52 -140 -40 -128 -28 -116 AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 29 jun. /2014
note 9: t is and t ih (input setup and hold) derating for all input signals the total t is (setup time) and t ih (hold time) required is calculated by adding the data sheet t is(base) and t ih(base) value to the ? t is and ? tih derating value respectively. example: t is (total setup time) = t is (base) + ? t is for slew rates in between the values listed in t ables 29, the derating values may obtained by linear interpolation.these values are typically not subjec t to production test. they are verified by design and characterization. table 29. derating values for ddr2-667, ddr2-800, ddr2-1066 tis and tih derating values for ddr2-667, ddr2-800, ddr2-1066 ck,ck# differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns tis tih tis tih tis tih units notes command/ address slew rate (v/ns) 4.0 +150 +94 +180 +124 +210 +154 ps 1 3.5 +143 +89 +173 +119 +203 +149 ps 1 3.0 +133 +83 +163 +113 +193 +143 ps 1 2.5 +120 +75 +150 +105 +180 +135 ps 1 2.0 +100 +45 +130 +75 +160 +105 ps 1 1.5 +67 +21 +97 +51 +127 +81 ps 1 1.0 0 0 +30 +30 +60 +60 ps 1 0.9 -5 -14 +25 +16 +55 +46 ps 1 0.8 -13 -31 +17 -1 +47 +29 ps 1 0.7 -22 -54 +8 -24 +38 +6 ps 1 0.6 -34 -83 -4 -53 +26 -23 ps 1 0.5 -60 -125 -30 -95 0 -65 ps 1 0.4 -100 -188 -70 -158 -40 -128 ps 1 0.3 -168 -292 -138 -262 -108 -232 ps 1 0.25 -200 -375 -170 -345 -140 -315 ps 1 0.2 -325 -500 -295 -470 -265 -440 ps 1 0.15 -517 -708 -487 -678 -457 -648 ps 1 0.1 -1000 -1125 -970 -1095 -940 -1065 ps 1 note 10: the maximum limit for this parameter is not a devic e limit. the device will operate with a greater value for this parameter, but system performanc e (bus turnaround) will degrade accordingly. note 11: min (t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be gr eater than the minimum specification limits for t cl and t ch ). note 12: t qh = t hp ? t qhs , where: t hp = minimum half clock period for any given cycl e and is defined by clock high or clock low (t ch , t cl ). t qhs accounts for: 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition fo llowed by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. note 13: t dqsq : consists of data pin skew and output pattern effe cts, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between dqs / dqs# and associated dq in any given cycle. note 14: t dal = wr + ru{ t rp [ns] / t ck [ns] }, where ru stands for round up.wr refers to the t wr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. note 15: the clock frequency is allowed to change during self ?refresh mode or precharge power-down mode. in case of clock frequency change during precharge power-down. note 16: odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resist ance is fully on. both are measured from t aond , which is interpreted as 2 clock cycles after the clock edge that registered a first odt high counting the actual input clock edges. note 17: odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-1066, if t ck (avg) = 1.875 ns is assumed, t aofd is 0.9375 ns (= 0.5 x 1.875 ns) after the second trailing clock edge counting from the clock edge t hat registered a first odt low and by counting the actual input clock edges. AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 30 jun. /2014
note 18: t hz and t lz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specific voltage level which spec ifies when the device output is no longer driving (t hz ), or begins driving (t lz ). note 19: t rpst end point and t rpre begin point are not referenced to a spec ific voltage level but specify when the device output is no longer driving (t rpst ), or begins driving (t rpre ). the actual voltage measurement points are not critical as long as the ca lculation is consistent. note 20: input waveform timing t ds with differential data strobe enabled mr[b it10]=0, is referenced from the input signal crossing at the v ih (ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the v il (ac) level to the differential data strobe cro sspoint for a falling signal applied to the device under test. dqs, dqs# signals must be monotonic between v il (dc)max and v ih (dc)min. note 21: input waveform timing t dh with differential data strobe enabled mr[bit10]=0, is referenced from the differential data strobe crosspoint to the input signal crossing at the v ih (dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il (dc) level for a rising signal applied to the device under test. dqs, dqs# signals must be monotonic between v il (dc)max and v ih (dc)min. note 22: input waveform timing is referenced fr om the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal applied to the device under test. note 23: input waveform timing is referenced fr om the input signal crossing at the v il (dc) level for a rising signal and v ih (dc) for a falling signal applied to the device under test. note 24: t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. note 25: t cke min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it ta kes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not tr ansition from its valid level during the time period of t is + 2 x t ck + t ih . note 26: if t ds or t dh is violated, data corruption may occur and the data must be re-written with valid data before a valid read can be executed. note 27: these parameters are measured from a command/addre ss signal (cke, cs#, ras#, cas#, we#, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck#) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. t jit (per), t jit (cc), etc.), as the setup and hold are relative to the clock signal crossing that latches t he command/address. that is, these par ameters should be met whether clock jitter is present or not. note 28: these parameters are measured from a data strobe signal (ldqs/udqs) crossing to its respective clock signal (ck/ck#) crossi ng. the spec values are not affected by the amount of clock jitter applied (i.e. t jit (per), t jit (cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. note 29: these parameters are measured from a data signal ((l /u) dm, (l/u) dq0, (l/u) dq1, etc.) transition edge to its respective data strobe signal (ldqs/udqs/ldqs#/udqs#) crossing. note 30: for these parameters, the ddr2 sdram device is characterized and verified to support tnparam = ru{tparam / t ck (avg)}, which is in clock cycles, assuming all i nput clock jitter specifications are satisfied. note 31: t dal [t ck ] = wr [t ck ] + trp [t ck ] = wr + ru {t rp [ps] / t ck (avg) [ps] }, where wr is the value programmed in the mode register set. note 32: new units, ?t ck (avg)? is introduced in ddr2-667, ddr2-800 and ddr2-1066. unit ?t ck (avg)? represents the actual t ck (avg) of the input clock under operation. note 33: input clock jitter spec parameter. these parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these par ameters apply to ddr2-667, ddr2-800 and ddr2-1066 only. the jitter specified is a random jitte r meeting a gaussian distribution. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 31 jun. /2014
table 30. input clock jitter spec parameter parameter symbol -18 -25 -3 units notes min. max. min. max. min. max. clock period jitter t jit ( per) -90 90 -100 100 -125 125 ps 33 clock period jitter during dll locking period t jit (per,lck) -80 80 -80 80 -100 100 ps 33 cycle to cycle clock period jitter t jit (cc) -180 180 -200 200 -250 250 ps 33 cycle to cycle clock period jitter during dll locking period t jit (cc,lck) -160 160 -160 160 -200 200 ps 33 cumulative error across 2 cycles t err (2per) -132 132 -150 150 -175 175 ps 33 cumulative error across 3 cycles t err (3per) -157 157 -175 175 -225 225 ps 33 cumulative error across 4 cycles t err (4per) -175 175 -200 200 -250 250 ps 33 cumulative error across 5 cycles t err (5per) -188 188 -200 200 -250 250 ps 33 cumulative error across n cycles, n=6...10, inclusive t err (6- 10per) -250 250 -300 300 -350 350 ps 33 cumulative error across n cycles, n=11...50, inclusive t err (11- 50per) -425 425 -450 450 -450 450 ps 33 duty cycle jitter t jit (duty) -75 75 -100 100 -125 125 ps 33 definitions: - t ck (avg) t ck (avg) is calculated as the average clock per iod across any consecutive 200 cycle window. () = ?? = ?? ?? j ck ck 1 /n tt n j avg where n=200 - t ch (avg) and t cl (avg) t ch (avg) is defined as the average high pulse width, as calculated across any cons ecutive 200 high pulses. () () () = ?? = ?? ?? j ch ch ck 1 / ttt n j avg n avg where n=200 t cl (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. () () () = ?? = ?? ?? j cl cl ck 1 / ttt n j avg n avg where n=200 t jit (duty) is defined as the cumulative set of t ch jitter and t cl jitter. t ch jitter is the largest deviation of any single t ch from t ch (avg). t cl jitter is the largest deviation of any single t cl from t cl (avg). - t jit (duty) = min/max of {t jit (ch), t jit (cl)} where, t jit (ch) = {t chi - t ch (avg) where i=1 to 200} t jit (cl) = {t cli - t cl (avg) where i=1 to 200} AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 32 jun. /2014
- t jit (per), t jit (per,lck) t jit (per) is defined as the largest dev iation of any single tck from t ck (avg). t jit (per) = min/max of {t cki - t ck (avg) where i=1 to 200} t jit (per) defines the single period jitte r when the dll is already locked. t jit (per,lck) uses the same definition for single period jitter, during the dll locking period only. t jit (per) and tjit (per,lck) are not guaranteed through final production testing. - t jit (cc), t jit (cc,lck) t jit (cc) is defined as the difference in clock period between two consecutive clock cycles: t jit (cc) = max of |t cki +1 ? t cki | t jit (cc) defines the cycle to cycle jitter when the dll is already locked. t jit (cc,lck) uses the same definition for cycle to cycle jitter, during the dll locking period only. t jit (cc) and tjit(cc,lck) are not guarant eed through final production testing. - t err (2per), t err (3per), t err (4per), t err (5per), t err (6-10per) and t err (11-50per) t err is defined as the cumulative error across multiple consecutive cycles from t ck (avg). () () () +? = ?? =? ?? ?? j 1 err ck ck 1 nper ttt in j navg where () () () () () () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? err err err err err err n=2 for 2 n=3 for 3 n=4 for 4 n=5 for 5 6 n 10 for 6 10 11 n 50 for 11 50 t t t t t t per per per per p er p er note 34: these parameters are specified per their average va lues, however it is understood that the following relationship between the average timing and the absolute inst antaneous timing holds at all times. (min andmax of spec values are to be used for calculations in the table below.) table 31. absolute clock period average values parameter symbol min. max. units absolute clock period t ck (abs) t ck (avg),min + t jit (per),min t ck (avg),max + t jit (per),max ps absolute clock high pulse width t ch (abs) t ch (avg),min * t ck (avg),min + t jit (duty),min t ch (avg),max * t ck (avg),max + t jit (duty),max ps absolute clock low pulse width t cl (abs) t cl (avg),min * t ck (avg),min + t jit (duty),min t cl (avg), max * t ck (avg),max + t jit (duty), max ps note 35: t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for tqh calculation is determined by the following equation; t hp = min ( t ch (abs), t cl (abs) ), where, t ch (abs) is the minimum of the actual instantaneous clock high time; t cl (abs) is the minimum of the ac tual instantaneous clock low time; note 36: t qhs accounts for: 1) the pulse duration distortion of on-chip clock circuits, which represents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dqs on one transition fo llowed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p- channel to n-channel variation of the output drivers AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 33 jun. /2014
note 37: t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half per iod of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} note 38: when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err (6-10per) of the input clock. ( output deratings are relative to the sdram input clock.) note 39: when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(per) of the input clock. (output deratings are relative to the sdram input clock.) note 40: when the device is operated with input clock jitter, this parameter needs to be derated by the actual t jit (duty) of the input clock. (output deratings are relative to the sdram input clock.) note 41: when the device is operated with input clock jitte r, this parameter needs to be derated by { - t jit (duty),max - t err (6-10per),max } and { - t jit (duty),min - t err (6-10per),min } of the actual input clock. (output deratings are relative to the sdram input clock.) note 42: for t aofd of ddr2-667/800/1066, t he 1/2 clock of t ck in the 2.5 x t ck assumes a t ch (avg), average input clock high pulse width of 0.5 relative to t ck (avg). t aof ,min and t aof ,max should each be derated by the same amount as the actual amount of t ch (avg) offset present at the dram input with respect to 0.5. note 43: if refresh timing is violated, data corruption may o ccur and the data must be re-writtern with valid data before a valid read can be executed. AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 34 jun. /2014
timing waveforms figure 8. initialization sequence after power-up ck ck# t ch cke command t cl t is odt t is nop pre all emr s mrs pre all ref ref mrs emr s emr s any cmd 400ns t rp t mrd t mrd t rp t mrd follow ocd flowchart t oit min 200 cycle dll enable dll reset ocd default ocd cal.mod e exit note 1: to guarantee odt off, v ref must be valid and a low level must be applied to the odt pin. t rfc t rfc figure 9. ocd drive mode ck# hi-z ck dqs dqs# dqs high for drive(1) cmd ocd calibration mode exit t oit enter drive mode emrs nop nop nop emrs dq dqs high & dqs# low for drive(1), dqs low & dqs# high for drive(0) dqs low for drive(0) t oit hi-z note : drive mode, both drive(1) and drive(0), is used for controllers to measure ddr2 sdram driver impedance.in this mode, al l outputs are driven out t oit after "enter drive mode" command and all output drivers are turned-off t oit after "ocd calibration mode exit" command. AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 35 jun. /2014
figure 10. ocd adjust mode ck# wl ck dqs_in dq_in dqs# t ds t dh cmd ocd calibration mode exit wr ocd adjust mode emrs nop nop nop nop nop emrs nop dt0 dt1 dt3 dt2 v ih(ac) v il(ac) v ih(dc) v il(dc) dm note 1: for proper operation of adjust mode, wl = rl - 1 = al + cl - 1t ck and t ds /t dh should be met as shown in the figure. note 2: for input data pattern for adjustment, dt0-dt3 is a fixed order and is not affected by burst type (i.e., sequential or interleave) figure 11. odt update delay timing-tmod ck updating rtt t is emrs nop nop nop nop nop cmd t aofd t mod, max t mod, min old setting new setting odt note 1: to prevent any impedance glitch on th e channel, the following conditions must be met: -t aofd must be met before issuing the emrs command. - odt must remain low for the entire duration of t mod window, until t mod , max is met. then the odt is ready for normal operation with the ne w setting, and the odt signal may be raised again to turned on the odt. note 2: emrs command directed to emr(1), which updates the information in emr(1)[a 6,a2], i.e. rtt (nominal). note 3: "setting" in this diagram is the register and i/o setting, not what is measured from outside. ck# AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 36 jun. /2014
figure 12. odt update delay timing-t mod , as measured from outside ck# ck rtt t is emrs cmd t aofd t mod, max old setting new setting odt nop nop nop nop nop t aond note 1: emrs command directed to emr(1), which update s the information in emr(1)[a6,a2], i.e. rtt (nominal). note 2: "setting" in this diagram is measured from outside. figure 13. odt timing for active standby mode ck# t0 internal term res. t is t is t aond ck t1 t2 t3 t4 t5 t6 cke odt v ih(ac) t is v il(ac) t aofd t aon,min t aon,max t aof,min t aof,max rtt AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. r eserves the r ight to change products or specification without notice rev. 1.4 37 jun. /2014
figure 14. odt timing for power-down mode ck# t0 internal term res. t is ck t1 t2 t3 t4 t5 t6 cke odt v ih(ac) t is v il(ac) t aofpd,max t aonpd,min rtt t aofpd,min t aonpd,max figure 15. odt timing mode switch at entering power-down mode ck# ck t is cke t aofd t aond odt t anpd t-5 t-4 t-3 t-2 t-1 t0 t1 t2 t3 t4 entering slow exit active power down mode or precharge power down mode. rtt internal term res. t is v il(ac) odt rtt internal term res. t is v il(ac) t aofpd max active & standby mode timings to be applied. power down mode timings to be applied. t is v ih(ac) rtt active & standby mode timings to be applied. t aonpd max t is v ih(ac) power down mode timings to be applied. rtt odt odt internal term res. internal term res. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the right to change products or specification without notice rev. 1.4 38 jun. /2014
figure 16. odt timing mode switch at exit power-down mode ck# ck t is cke t aofd t aond odt t axpd t0 t1 t4 t5 t6 t7 t8 t9 t10 t11 exiting from slow active power down mode or precharge power down mode. internal term res. t is v il(ac) odt internal term res. t is v il(ac) active & standby mode timings to be applied. power down mode timings to be applied. t is v ih(ac) active & standby mode timings to be applied. t aonpd max t is v ih(ac) power down mode timings to be applied. odt odt internal term res. internal term res. rtt t aofpd max v ih(ac) rtt rtt rtt figure 17. bank activate command cycle (t rcd =3, al=2, t rp =3, t rrd =2, t ccd =2) ck# t0 t1 t2 t3 tn tn+1 tn+2 internal ras# - cas# delay (>=t rcd min ) cas# - cas# delay time (t ccd ) t rcd = 1 read begins tn+3 bank a row addr. bank a col. addr. bank b row addr. bank b col. addr bank a addr. bank b addr. bank a row addr. additive latency delay (al) bank a activate bank a post cas# read bank b activate bank b post cas# read bank a precharge bank b precharge bank a activate ras# - ras# delay time (>=t rrd ) bank active (>=t ras ) bank precharge time (>=t rp ) ras# cycle time (>=t rc ) address command ck AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. r eserves the r ight to change products or specification without notice rev. 1.4 39 jun. /2014
figure 18.1. posted cas# operation: al=2 read followed by a write to the same bank ck# cmd al=2 -1 1 2 3 4 5 6 7 8 9 0 10 11 12 active a-bank read a-bank write a-bank cl=3 wl=rl-1=4 dout 0 dout 1 dout 2 dout 3 din 0 din 1 din 2 din 3 rl=al+cl=5 >=t rcd [ al=2 and cl=3, rl= (al+cl)=5, wl= (rl-1)=4, bl=4] dqs dq ck dqs# figure 18.2. posted cas# operation: al=0 read followed by a write to the same bank ck# cmd al=0 -1 1 2 3 4 5 6 7 8 9 0 10 11 12 active a-bank read a-bank write a-bank cl=3 wl=rl-1=2 dout 0 dout 1 dout 2 dout 3 din 0 din 1 din 2 din 3 rl=al+cl=3 >=t rcd [ al=0 and cl=3, rl= (al+cl)=3, wl= (rl-1)=2, bl=4] dqs dq ck dqs# AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 40 jun. /2014
figure 19. data output (read) timing ck# ck dq t dqsq max ck t ch t rpst t rpre dqs t cl dqs# dqs q q q t qh q t qh t dqsq max dqs# figure 20.1. burst read operation: rl=5 (al=2, cl=3, bl=4) ck ck# dqs cmd dqs t0 t1 t2 t3 t4 t5 t6 t7 t8 posted cas# read a nop nop nop nop nop nop nop nop =< t dqsck dout a0 dout a1 dout a2 dout a3 al=2 cl=3 rl=5 dqs# figure 20.2. burst read operation: rl=3 (al=0, cl=3, bl=8) ck ck# dqs cmd dqs t0 t1 t2 t3 t4 t5 t6 t7 t8 read a nop nop nop nop nop nop nop nop dout a0 dout a1 dout a2 dout a3 cl=3 rl=3 dqs# =< t dqsck dout a4 dout a5 dout a6 dout a7 AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 41 jun. /2014
figure 21. burst read followed by burst write: rl=5, wl= (rl-1) =4, bl=4 ck ck# dqs cmd dqs t0 t1 tn-1 tn tn+1 tn+2 tn+3 tn+4 tn+5 post cas# read a nop nop post cas# write a nop nop nop nop nop dout a 0 rl=5 dqs# t rtw (read to write turn around time) wl = rl-1 = 4 dout a 1 dout a 2 dout a 3 din a 0 din a 1 din a 2 din a 3 note : the minimum time from the burst read command to the burst write command is defined by a read-to-write- turn-around-time, which is 4 clocks in cas e of bl = 4 operation, 6 clocks in case of bl = 8 operation. figure 22. seamless burst read operation: rl=5, al=2, cl=3, bl=4 ck ck# dqs cmd dqs t0 t1 t2 t3 t4 t5 t6 t7 t8 post cas# read a nop post cas# read b nop nop nop nop nop nop dout a0 al=2 dqs# dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 cl=3 rl=5 note : the seamless burst re ad operation is supported by enabling a read command at every other clock for bl = 4 operation, and every 4 clock for bl =8 operation. this operation is allowed regardless of same or different banks as long as the banks are activated. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 42 jun. /2014
figure 23. read burst interrupt timing: (cl=3, al=0, rl=3, bl=8) ck# ck cmd read a nop read b nop nop nop nop nop nop nop a0 a1 a2 a3 b0 b1 b2 b3 b4 b5 b6 b7 dqs dqs# dqs note 1: read burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited. note 2: read burst of 8 can only be interrupted by another read command. read burst interruption by write command or precharge command is prohibited. note 3: read burst interrupt must occur exactly two clocks after previous read command. any other read burst interrupt timings are prohibited. note 4: read burst interruption is allowed to any bank inside dram. note 5: read burst with auto precharge enabled is not allowed to interrupt. note 6: read burst interruption is allowed by another read with auto precharge command. note 7: all command timings are referenced to burst length set in the mode register. they are not referenced to actual burst. for example, minimum read to precharge timing is al+bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). figure 24. data input (write) timing dqs# dq dqs t dqsh t wpre dqs dm t dqsl t wpsl v il(ac) v ih(ac) d d v il(dc) v ih(dc) d d dmin dmin dqs# dmin v ih(ac) v il(ac) dmin v ih(dc) v il(dc) t ds t ds t dh t dh AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 43 jun. /2014
figure 25.1. burst write operation: rl=5 (al=2, cl=3), wl=4, bl=4 ck# ck t dqss cmd case 1: with t dqss (max) >=t wr t0 t1 t2 t3 t4 t5 t6 t7 tn posted cas# write a nop nop nop nop nop nop nop precharge t dss t dqss t dss completion of the burst write wl = rl-1 =4 dna 0 dna 1 dna 2 dna 3 dqs dqs# >=t wr wl = rl-1 =4 dna 0 dna 1 dna 2 dna 3 dqs dqs# t dqss t dsh t dqss t dsh case 2: with t dqss (min) dqs dqs figure 25.2. burst write operation: rl=3 (al=0, cl=3), wl=2, bl=4 ck# ck <=t dqss cmd >=t wr t0 t1 t2 t3 t4 t5 tm tm+1 tn write a nop nop nop nop nop precharge nop bank a activate completion of the burst write wl = rl-1 =2 dna 0 dna 1 dna 2 dna 3 dqs dqs# dqs >=t rp AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 44 jun. /2014
figure 26. burst write followed by burst read: rl=5 (al=2, cl=3, wl=4, t wtr =2, bl=4) ck# ck cke t0 t1 t4 t5 t6 t7 t8 t9 t2 t3 nop nop nop nop post cas# read a nop nop nop nop dqs al=2 dqs# wl = rl-1 = 4 dqs# dqs cl=3 rl=5 >=t wtr dna 0 dna 1 dna 2 dna 3 dout a 0 dq note : the minimum number of clock from the burst write command to the burst read co mmand is [cl-1 + bl/2 + t wtr ]. this t wtr is not a write recovery time (t wr ) but the time required to transfer the 4 bit write data from the inpu t buffer into sense amplifiers in the array. t wtr is defined in the timing para meter table of this standard. write to read = cl-1+bl/2+t wtr figure 27. seamless burst write operation rl=5, wl=4, bl=4 ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# write a nop post cas# write b nop nop nop nop nop nop dqs dqs# wl = rl-1 = 4 dqs# dqs dna 0 dna 1 dna 2 dna 3 dq dnb 0 dnb 1 dnb 2 dnb 3 note : the seamless burst write operation is supporte d by enabling a write comma nd every other clock for bl= 4 operation, every four clocks for bl = 8 operatio n. this operation is allowed regardless of same or different banks as long as the banks are activated. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 45 jun. /2014
figure 28. write burst interrupt timing: (cl=3, al=0, rl=3, wl=2, bl=8) ck# ck cmd nop write a nop write b nop nop nop nop nop nop a0 a1 a2 a3 b0 b1 b2 b3 b4 b5 b6 b7 dqs dqs# dqs note 1: write burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited. note 2: write burst of 8 can only be interrupted by another write command. write burst interruption by read command or precharge command is prohibited. note 3: write burst interrupt must occur exactly two clocks after previous write command. any other write burst interrupt timings are prohibited. note 4: write burst interruption is allowed to any bank inside dram. note 5: write burst with auto precharge enabled is not allowed to interrupt. note 6: write burst interruption is allowed by another write with auto precharge command. note 7: all command timings are referenced to burst length set in the mode register. they are not referenced to actual burst. for example, minimum write to precharge timing is wl + bl/2 + twr where twr starts with the rising clock after the uninterrupted burst end and not from the end of actual burst end. AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 46 jun. /2014
figure 29. write data mask dq dqs dm dqs# t ds v ih(ac) v ih(dc) v il(ac) v il(dc) t dh t ds v ih(ac) v ih(dc) v il(ac) v il(dc) t dh ck# ck command dqs dqs# dq write t wr wl t dqss t dqss dm case 2: max t dqss dqs dqs# dq dm case 1: min t dqss data mask function, wl=3, al=0, bl=4 shown data mask timing AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 47 jun. /2014
figure 30.1. burst read operation followed by precharge: (rl=4, al=1, cl=3, bl=4, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop precharge nop nop nop bank a active nop dqs dqs# al+bl'/2 clks douta 0 douta 1 douta 2 douta 3 dq >=t rp al=1 cl=3 rl=4 >=t ras >=t rtp cl=3 figure 30.2.burst read operation followed by precharge: (rl=4, al=1, cl=3, bl=8, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop precharge a nop nop nop dqs dqs# rl= 4 dout a 0 dout a 1 dout a 2 dout a 3 dq's al + bl/2 clks cl = 3 al = 1 first 4-bit prefetch >=t rtp second 4-bit prefetch dout a 4 dout a 5 dout a 6 dout a 7 AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 48 jun. /2014
figure 30.3. burst read operation followed by precharge: (rl=5, al=2, cl=3, bl=4, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop precharge a nop nop bank a activate nop dqs dqs# rl= 5 dout a 0 dout a 1 dout a 2 dout a 3 dq's al + bl/2 clks cl = 3 al = 2 >=t ras >=t rp cl = 3 >=t rtp figure 30.4. burst read operation followed by precharge: (rl=6, al=2, cl=4, bl=4, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop precharge a nop nop bank a activate nop dqs dqs# rl= 6 dout a 0 dout a 1 dout a 2 dout a 3 dq's al + bl/2 clks cl = 4 al = 2 >=t ras >=t rp cl = 4 >=t rtp AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the r ight to change products or specification without notice rev. 1.4 49 jun. /2014
figure 30.5. burst read operation followed by precharge: (rl=4, al=0, cl=4, bl=8, t rtp >2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop precharge a nop nop bank a activate dqs dqs# rl= 4 dout a 0 dout a 1 dout a 2 dout a 3 dq's al + 2 + max( t rtp , 2 t ck )* cl = 4 al = 0 first 4-bit prefetch >=t rtp second 4-bit prefetch dout a 4 dout a 5 dout a 6 dout a 7 >=t rp >=t ras *: rounded to next integer. figure 31.1. burst write operation followed by precharge: wl= (rl-1) =3 ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# write a nop nop nop nop nop nop nop precharge a dqs dqs# dna 0 dna 1 dna 2 dna 3 dq's >=t wr wl= 3 completion of the burst write AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the r ight to change products or specification without notice rev. 1.4 50 jun. /2014
figure 31.2. burst write followed by precharge: wl= (rl-1) =4 ck# ck cmd t0 t1 t4 t5 t6 t7 t9 t2 t3 post cas# write a nop nop nop nop nop nop nop precharge a dqs dqs# dna 0 dna 1 dna 2 dna 3 dq's >=t wr wl= 4 completion of the burst write figure 32.1. burst read operation with auto precharge: (rl=4,al=1, cl=3, bl=8, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop nop nop nop bank a activate dqs dqs# rl= 4 dout a 0 dout a 1 dout a 2 dout a 3 dq's al + bl/2 clks cl = 3 al = 1 autoprecharge >=t rtp second 4-bit prefetch dout a 4 dout a 5 dout a 6 dout a 7 >= t rp t rtp precharge begins here first 4-bit prefetch AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 51 jun. /2014
figure 32.2. burst read operation with auto precharge: (rl=4, al=1, cl=3, bl=4, t rtp >2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop nop nop bank a activate nop dqs dqs# douta 0 douta 1 douta 2 douta 3 dq's cl= 3 autoprecharge >= al+t rtp +t rp al= 1 rl= 4 t rtp t rp first 4-bit prefetch precharge begins here figure 32.3. burst read operation with auto precharge followed by activation to the same bank (t rc limit): rl=5(al=2, cl=3, internal t rcd =3, bl=4, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop nop nop nop bank a activate dqs dqs# douta 0 douta 1 douta 2 douta 3 dq's cl= 3 >=t ras (min) al= 2 rl= 5 >= t rc cl=3 a10= 1 auto precharge begins >=t rp AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. r eserves the r ight to change products or specification without notice rev. 1.4 52 jun. /2014
figure 32.4. burst read operation with auto precharge followed by an activation to the same bank (t rp limit): (rl=5 (al=2, cl=3, internal t rcd =3, bl=4, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop nop nop bank a activate nop dqs dqs# douta 0 douta 1 douta 2 douta 3 dq's cl= 3 >=t ras (min) al= 2 rl= 5 >= t rc cl=3 a10= 1 auto precharge begins >= t rp figure 33.1. burst write with auto-precharge (t rc limit): wl=2, wr=2, bl=4, t rp =3 ck# ck cmd t0 t1 t4 t5 t6 t7 tm t2 t3 post cas# wra bank a nop nop nop nop nop nop nop bank a active dqs dqs# dna 0 dna 1 dna 2 dna 3 dq's auto precharge begins wl= rl-1=2 completion of the burst write a10 = 1 >=wr >=t rp >=t rc AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 53 jun. /2014
figure 33.2. burst write with auto-precharge (wr+t rp ): wl=4, wr=2, bl=4, t rp =3 ck# ck cmd t0 t3 t6 t7 t8 t9 t12 t4 t5 post cas# wra bank a nop nop nop nop nop nop nop bank a active dqs dqs# dna 0 dna 1 dna 2 dna 3 dq's auto precharge begins wl= rl-1=4 completion of the burst write a10 = 1 >=wr >=t rp >=t rc figure 34. refresh command ck# ck cke t0 t1 tm tn tn+1 t2 t3 precharge nop nop ref ref nop any cmd high >=t rp >=t rfc >=t rfc AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 54 jun. /2014
figure 35. self refresh operation ck# ck cke t0 t1 t5 tm t2 t3 cmd >=t xsnr t rp* t ch t cl t ck t4 t6 tn >=t xsrd t is v il(ac) v ih(ac) t is nop self refresh odt t aofd t is v il(ac) t ih t is t ih t is t ih v il(dc) v il(ac) v ih(ac) v ih(dc) nop nop valid note 1 device must be in the "all banks idle" state prior to entering self refresh mode. note 2 odt must be turned off t aofd before entering self refresh mode, and can be turned on again when t xsrd timing is satisfied. note 3 t xsrd is applied for read or a read with autoprecharge command. t xsnr is applied for any command except a read or a read with autoprecharge command. figure 36. basic power down entry and exit timing diagram ck# ck command cke valid t ih t cke min t ih t ih t ih t is t is t is nop nop nop valid valid or nop t xp, t xard t xards t cke(min) exit power-down mode don't care enter power-down mode figure 37.1.cke intensive environment ck# cke t cke note: dram guarantees all ac and dc timing & voltage specifications and proper dll operation with intensive cke operation ck t cke t cke t cke AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 55 jun. /2014
figure 37.2.cke intensive environment ck# cke t cke note: the pattern shown above can repeat over a long period of time. with this pattern, dram guarantees all ac and dc timing & voltage specifications and dll operation with temperature and voltage drift ck t cke t cke t cke t xp t xp t refi = 3.9 s ref ref cmd figure 38. read to power-down entry ck# cmd bl=4 t0 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 t1 tx+8 tx+9 rd q al+cl read operation starts with a read command and dqs cke ck dqs# cke should be kept high until the end of burst operation t is q q q dq ck# cmd bl=8 t0 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 t1 tx+8 tx+9 rd q al+cl dqs cke ck dqs# cke should be kept high until the end of burst operation t is q q q dq q q q q AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620- 9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 56 jun. /2014
figure 39. read with autoprecharge to power-down entry ck# cmd bl=4 t0 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 t1 tx+8 tx+9 rda q al+cl dqs cke ck dqs# cke should be kept high until the end of burst operation t is q q q dq ck# cmd bl=8 t0 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 t1 tx+8 tx+9 rd q al+cl dqs cke ck dqs# cke should be kept high until the end of burst operation t is q q q dq q q q q pre al+bl/2 with t rtp = 7.5ns & t ras min satisfied pre start internal precharge al+bl/2 with t rtp = 7.5ns & t ras min satisfied figure 40. write to power-down entry ck# cmd bl=4 t0 tm tm+1 tm+2 tm+3 tx tx+1 tx+2 ty ty+1 t1 ty+2 ty+3 wr q wl dqs cke ck dqs# t is q q q dq ck# cmd bl=8 t0 tm tm+1 tm+2 tm+3 tm+4 tm+5 tx tx+1 tx+2 t1 tx+3 tx+4 wr q wl dqs cke ck dqs# q q q dq q q q q t wtr t is t wtr AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 57 jun. /2014
figure 41. write with autoprecharge to power-down entry ck# cmd bl=4 t0 tm tm+1 tm+2 tm+3 tx tx+1 tx+2 tx+3 tx+4 t1 tx+5 tx+6 wra q wl dqs cke ck dqs# t is q q q dq ck# cmd bl=8 t0 tm tm+1 tm+2 tm+3 tm+4 tm+5 tx tx+1 tx+2 t1 tx+3 tx+4 wra q wl dqs cke ck dqs# q q q dq q q q q wr*1 t is pre wr*1 pre start internal precharge *1: wr is programmed through mrs figure 42. refresh command to power-down entry ck# cmd t0 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 ref cke ck t is t11 cke can go to low one clock after an auto-refresh command figure 43. active command to power-down entry cmd t0 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 act cke t is t11 cke can go to low one clock after an active command AS4C32M16D2A-25BCN alliance m emory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 58 jun. /2014
figure 44. precharge/precharge-all command to power-down entry cmd t0 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 pr or pra cke t is t11 cke can go to low one clock after a precharge or precharge all command figure 45. mrs/emrs command to power-down entry cmd t0 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 mrs or emrs cke t is t11 t mrd figure 46. asynchronous cke low event ck# ck cke t ck t delay cke asynchronously drops low clocks can be turned off after this point t is stable clocks figure 47. clock frequency change in precharge power down mode ck# cmd t0 t2 t4 tx tx+1 ty ty+1 ty+2 ty+3 ty+4 t1 tz frequency change occurs here t rp cke odt ck nop nop nop nop dll reset nop valid 200 clocks t aofd minimum 2 clocks required before changing frequency stable new clock before power down exit t xp t is t is t ih odt is off during dll reset AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc . r eserves the r ight to change products or specification without notice rev. 1.4 59 jun. /2014
figure 48. 84-ball 8x12.5x1.2mm(max.) fbga package outline drawing information top view bottom view side view pin a1 index detail : "a" symbol dimension in inch dimension in mm min nom max min nom max a -- -- 0.047 -- -- 1.20 a1 0.010 -- 0.016 0.25 -- 0.40 a2 0.030 0.031 0.033 0.75 0.80 0.85 a3 0.005 0.006 0.007 0.125 0.155 0.185 d 0.311 0.315 0.319 7.9 8.0 8.1 e 0.488 0.492 0.496 12.4 12.5 12.6 d1 -- 0.252 -- -- 6.40 -- e1 -- 0.441 -- -- 11.2 -- f -- 0.126 -- -- 3.2 -- e -- 0.031 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50 d2 -- -- 0.081 -- -- 2.05 AS4C32M16D2A-25BCN alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. r eserves the r ight to change products or specification without notice rev. 1.4 60 jun. /2014
AS4C32M16D2A-25BCN ordering information alliance organization package operating temp speed mhz AS4C32M16D2A-25BCN 32m x 16 1.8v 84 ball fbga commercial 400 part numbering system as4c 25 b=bga package c n sdram ddr2 32m16=32mx16 d 2 a=ddr2 speed 400mhz 84 ball bga temperature range c = commercial (0 - 95c) n = lead free rohs compliant part vcc range 32m16d2a alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 a lliance memory inc . reserves the right to change products or specific ation without notice rev. 1.4 61 jun. /2014

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